Forum Discussion
DPond
New Contributor
6 years agoHi Wolfgang,
I am using Quartus version 18.1 Lite. I used your suggestion (check the Enable real-time ISP...) and generated a combined jbc file. The result was successful, now both FPGAs get configured when we execute that .jbc file using altera Stapl code on our embedded system.
Thank you for your help.
-Dan