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Altera_Forum
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14 years ago

is VHDL unsafe with state machine?

Typical VHDL state machine is to define a type that consist of states, then use that type in a signal. But if someone (not me, no way! ;-)) forget to put a reset state, the state machine continues to...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I think the original question is sensible as there is some ambiguity here (though it is tool related issue) that even if fpga guarantees zero power up state of most flips, then that does not means guaranteeing start up state registers which could be encoded as some nonzero value.

So, yes power reset is essential and your circuit will not start same otherwise.