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Altera_Forum's avatar
Altera_Forum
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14 years ago

is VHDL unsafe with state machine?

Typical VHDL state machine is to define a type that consist of states, then use that type in a signal. But if someone (not me, no way! ;-)) forget to put a reset state, the state machine continues to...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I don't want to drag discussion back to some posts in 2008. But, an issue was raised that "when others" is ignored by most tools by default unless you override it, because it takes too much logic. Thus a reset is essential for power up case. For critical applications it must be safe in real time as well and so when others must be there fitted.

Does that mean "when others" of state machines only or any case statement, I don't know and I don't think so.