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Altera_Forum
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15 years ago

Is there any virtual jtag C API functions?

Dear All, I am using Altera Virtual Jtag to develop my own debug tool on FPGA. I notice that on host PC, I have to write Tcl script and evaluated it through quartus_stp.exe shell prog...
Altera_Forum's avatar
Altera_Forum
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15 years ago

But is there any method of exercising the JTAG pins of the buried SOPC from the top level of a design in a RTL simulation?

I recognise the system console commands in the provided example, but this is for the actual device isn't it? (exercising a programmed device for real).

This method would be fine for what I am tring to do, but I need to exercise the buried SOPC registers through the JTAG UART SOPC component in a RTL simulation (using my VHDL testbench and/or TCL if possible).

Please advise.

Thanks,

Winston.