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Altera_Forum
Honored Contributor
19 years agoIf you don't want Nios, Serial Flashloader (SFL) is the solution you are asking for. This is a bridge function that allows the FPGA JTAG port to program the EPCS device that is attached to the FPGA. You can either have it present in your design all the time using the megafunction or QII can temporarily load a Serial Flash Loader image to the FPGA for you to bridge the programming of the EPCS through JTAG.
This app note should have the details of both although its a little tough to understand. You can convert a SOF (for your new design that you want in the EPCS) into a JIC file. That JIC file serves two function -> first part is the SFL bridging image which loads into the FPGA, the 2nd part of that file is the EPCS data that will pass through the bridge. Quartus should do this for you. http://www.altera.com/literature/an/an370.pdf