Is SystemVerilog Catching on for Design

--- Quote Start ---

Hi guys, well i started directly on Verilog, and i have been doing it for 4 years now, i am also curious about SV, what will it really do for my designs?

as far as i could see its a change to a more C-like structure of coding, but will it actually improve the code itself?

--- Quote End ---

What, If Anything, In SystemVerilog Will Help Me With FPGA-based Design?

http://www.sutherland-hdl.com/papers.php

sorry to hear that, at least you have a plan.

i don't see much different between your document and the actual IEEE document.

Actualy, my current company is shutting down this design center. I have been offered (and accepted) a graduate assistant ship with Boise State University (go Broncos!).. I will be working on my MSEE for a couple of years... I guess I will have it then.

Ed

this document looks excellent, there are many examples.

maybe you should take a study day at a local university with IEEE access. :)

Yes, that sounds correct. I have not been able to get the spec.. requires access to the IEEE library. Expensive,and my company does not pay for it..

I have the SystemVerilog 3.1a Language Reference Manual (LRM) Accelllera's Extensions to Verilog.

http://www.vhdl.org/sv/systemverilog_3.1a.pdf

This seems to be very complete.

You need to keep in mind what is synthesizable and what is not. From the Altera documents - quartus handbook, page 405 (of current manual).

The best way to approach it is check it.. if you are not sure of a particular structure, then write a simple test and see if quartus will synthesize it..

Some things work, but take some figuring out.. Quartus supports "generic" interfaces, but it took me time to figure out HOW to do it.... they provide NO examlples (hint hint), just state they work...

Cheers.

thanks very much. is this the right spec to look at:

ieee standard for systemverilog- unified hardware design, specification, and verification language

I have used the SystemVerilog Spec and "System Verilog for Design".

SV for Design is an execllent book. It is written for someone familiar with Verilog to be able to start using the new SystemVerilog capabilities. It takes a slow approach, and you can definitly take small steps into the world of SV. It isn't an all-or-nothing approach.. start using a few basic features, and add more as you find need.

Ed

ed,

do you have any texts you could recommend about SystemVerilog?

--- Quote Start ---

Hi guys, well i started directly on Verilog, and i have been doing it for 4 years now, i am also curious about SV, what will it really do for my designs?

as far as i could see its a change to a more C-like structure of coding, but will it actually improve the code itself?

--- Quote End ---

Man, I see a lot of miss-information, uninformed information in these forums.

SystemVerilog can have a huge effect on your designs, in a very positive way. It is not about "structures".

I have one word, repeated multiple times, interfaces, interfaces, interfaces.

Learn them, use them. They will single-handedly improve your design significantly. Quartus II supports them and they are a huge benefit.

I shudder to think how I would live without them now that I have learned to use them. My own question to Altera is.. well, that is a question for a different post.

I might have to post some examples or something.. it just seems like nobody knows that interfaces are.

Ed