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Altera_Forum
Honored Contributor
Honored ContributorIs SystemVerilog Catching on for Design
Hello, I'd like to know how how popular SystemVerilog is today, how many people are switching from Verilog to SV? I'm pretty much a AHDL guy but I've been trying to teach myself Verilog. One thing th...
Altera_ForumHonored Contributor
Honored ContributorYes, that sounds correct. I have not been able to get the spec.. requires access to the IEEE library. Expensive,and my company does not pay for it..
I have the SystemVerilog 3.1a Language Reference Manual (LRM) Accelllera's Extensions to Verilog. http://www.vhdl.org/sv/systemverilog_3.1a.pdf This seems to be very complete. You need to keep in mind what is synthesizable and what is not. From the Altera documents - quartus handbook, page 405 (of current manual). The best way to approach it is check it.. if you are not sure of a particular structure, then write a simple test and see if quartus will synthesize it.. Some things work, but take some figuring out.. Quartus supports "generic" interfaces, but it took me time to figure out HOW to do it.... they provide NO examlples (hint hint), just state they work... Cheers.
