Is SystemVerilog Catching on for Design

Hi Joe -

I'm a former AHDL guy, now Verilog guy. I just started learning SystemVerilog a couple weeks ago. It is very much 'Verilog with some add-ons' rather than a new beast. The addons are GREAT if you find yourself wanting C-like structures / datatypes. There are some nice new features for doing constrained random simulation, and asserts. A couple of minor annoyances in the Verilog syntax are removed.

I started off with this link from some language buffs. It's a little bit out of date, but it sums up the Verilog / SV changes pretty well.

http://www.sutherland-hdl.com/papers/2003-systemverilog_white_paper.pdf

The SV support in Modelsim and Quartus is pretty good. You can tell it isn't quite as polished as the straight Verilog, but pretty civilized.

-Gregg

Gregg,

Hello, thanks for the link and the encouragement.

joe306

If you are to use HDL language I recommand SystemVerilog. Learn verilog first then jump all in to system verilog. You just have more with SystemVerilog.

Here is a book about SystemVerilog for design. It's not a great book,but it will do for now

systemverilog for design second edition: a guide to using systemverilog for hardware design and modeling (hardcover) by stuart sutherland, simon davidmann, peter flake, and p. moorby (hardcover - jul 20, 2006) make sure you get the second edition

Hi guys, well i started directly on Verilog, and i have been doing it for 4 years now, i am also curious about SV, what will it really do for my designs?

as far as i could see its a change to a more C-like structure of coding, but will it actually improve the code itself?

hi guys,

actually SystemVerilog is not an HDL language for designing and synthesizing a circuit. it "adds" some system-level features to a lower-level language like verilog, which is good for describing a system or performing verification of the designs.

in contrast, a language like SystemC adds a lower-level features to higher-level language (C++) to accomplish the same thing.

adel

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Hi guys, well i started directly on Verilog, and i have been doing it for 4 years now, i am also curious about SV, what will it really do for my designs?

as far as i could see its a change to a more C-like structure of coding, but will it actually improve the code itself?

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Man, I see a lot of miss-information, uninformed information in these forums.

SystemVerilog can have a huge effect on your designs, in a very positive way. It is not about "structures".

I have one word, repeated multiple times, interfaces, interfaces, interfaces.

Learn them, use them. They will single-handedly improve your design significantly. Quartus II supports them and they are a huge benefit.

I shudder to think how I would live without them now that I have learned to use them. My own question to Altera is.. well, that is a question for a different post.

I might have to post some examples or something.. it just seems like nobody knows that interfaces are.

Ed

ed,

do you have any texts you could recommend about SystemVerilog?

I have used the SystemVerilog Spec and "System Verilog for Design".

SV for Design is an execllent book. It is written for someone familiar with Verilog to be able to start using the new SystemVerilog capabilities. It takes a slow approach, and you can definitly take small steps into the world of SV. It isn't an all-or-nothing approach.. start using a few basic features, and add more as you find need.

Ed

thanks very much. is this the right spec to look at:

ieee standard for systemverilog- unified hardware design, specification, and verification language