is possible translate a design created in graphic entry to verilog?

we have a project created using graphical entry (blocks) in QUARTUSII and we want edit it in FPGA ADVANTAGE environment of MENTOR GRAPHICS.

the question is : is possible translate a project in graphical entry to verilog or VHDL ? how can i do that?

Graphical entry is not portable , then i have to edit all components in FPGA ADVANTAGE , in the case in graphical entry due the LPM, it is very tiring and dangerous .

can anybody help ?

best regard

Claudionor

SAO PAULO / BRAZIL