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Altera_Forum's avatar
Altera_Forum
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18 years ago

is possible translate a design created in graphic entry to verilog?

we have a project created using graphical entry (blocks) in QUARTUSII and we want edit it in FPGA ADVANTAGE environment of MENTOR GRAPHICS. the question is : is possible translate a project in g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

This can be done from Quartus file menu under Create/Update Create HDL Design File for Current File.