Is "phase shift" or "delay" a constant whatever the frequency is?

Thanks for your reply sstrell,

I'm using latest version of Quartus Lite but still need version 14SP1 to use the MegaWizzard Function Plugin.

The puprose of my project is to design a RAM controller so I need to specify timing constraints on RAM ports in order to make sure ISSI_SDRAM timing are met.

I had a look to a lot of document and the mentioned document is the only one to specify that delay. Unfortunately, the value is given at 50MHz and nothing is said about higher frequency (DRAM datasheet only specify 2 working frequence: 100MHz and 143MHz and I decided to go for 143MHz).

I would like to understand the reason of that delay. If it is because the wire is long and the signal then needs more time to reach registers inside the DRAM or if new clocks are generated inside the DRAM but a fix delay of 3ns can be observed.....:-s Probably something else?

Do you know more than me about that requirement?

Thanks,

Jean