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Altera_Forum's avatar
Altera_Forum
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12 years ago

Is my Cyclone 2 in self protection mode ?

Hi all

I have a relatively simple application running on a Cyclone 2 EP2c8, where the FPGA is the master for high speed bidirectional communication signals to another module.

During operation at my customer, occasionally the FPGA goes into a state where it requires a reset to continue operation.

I believe this occurs when the output pin is driving too much current due to the other module driving against the FPGA (timing issue).

I was unable to find any documentation on the behavior of the FPGA in the case where the I/O current limits are exceeded.

My question is :

Does such internal protection circuitry exist which sends the FPGA to some fault mode, where it stays until a reset is generated.

If so, is it possible to modify the behavior to control the behavior (reset automatically after some time etc).

Regards,

Adrian

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Does such internal protection circuitry exist

    --- Quote End ---

    No.

    The FPGA isn't designed for operation beyond it's maximum ratings, which involves a risk of permanent damage. You have to avoid it by correct hardware and logic design.

    There's are many possible explanations for "locked" state of FPGA logic. Unhandled illegal states caused by timing violations are the most likely one in my view.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thanks for the clarification. I think you are correct that it is probably due to a timing issue with the FPGA ending up in a undefined state. Cheers.

    --- Quote Start ---

    No.

    The FPGA isn't designed for operation beyond it's maximum ratings, which involves a risk of permanent damage. You have to avoid it by correct hardware and logic design.

    There's are many possible explanations for "locked" state of FPGA logic. Unhandled illegal states caused by timing violations are the most likely one in my view.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Thanks for the clarification. I think you are correct that it is probably due to a timing issue with the FPGA ending up in a undefined state. Cheers.

    --- Quote End ---

    Verified the issue is due to a synchronization issue between a signal at a pin (asynchronous) and internally clocked signal. Adding a synchronous delay to pin signal before the logic operation removed the need for reset.

    Thanks,

    Adrian