Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThanks for the clarification. I think you are correct that it is probably due to a timing issue with the FPGA ending up in a undefined state. Cheers.
--- Quote Start --- No. The FPGA isn't designed for operation beyond it's maximum ratings, which involves a risk of permanent damage. You have to avoid it by correct hardware and logic design. There's are many possible explanations for "locked" state of FPGA logic. Unhandled illegal states caused by timing violations are the most likely one in my view. --- Quote End ---