Forum Discussion
BHoey
New Contributor
New ContributorIs LVDS supported on the dedicated clock input of the Cyclone 10 GX 3.3V IO Bank?
I do not see where it says this is not allow (handbook, pin connection guidelines) but Quartus is not presenting LVDS as an option. The dedicated clock inputs have always supported LVDS in Altera FP...
JonWay_altera
Frequent Contributor
Frequent ContributorHi BHoey,
I understand your problem statement, and I have crosschecked it with the Pin Planner and pinout files.
For Cyclone 10 GX and Arria 10, the IO architecture works differently.
First, determine what IO standard you are using,
Example: You cannot place LVDS IO standard in a 3VIO bank.
For full list of what IO standard can place in which bank, you can refer to
how to know what bank is LVDS IO bank or 3V IO bank?
Bank 2L is 3V IO bank
Then once you assigned the IO standard to its bank, what VCCIO, VCCPT, VREF, VTT should be used?
