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BHoey's avatar
BHoey
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7 years ago

Is LVDS supported on the dedicated clock input of the Cyclone 10 GX 3.3V IO Bank?

I do not see where it says this is not allow (handbook, pin connection guidelines) but Quartus is not presenting LVDS as an option. The dedicated clock inputs have always supported LVDS in Altera FP...
BHoey's avatar
BHoey
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7 years ago

This is the 3V IO Bank. LVDS does not show as an option on the dedicated clock inputs in the 3V bank. The handbook is not clear on dedicated clock io standard options.

The dedicated IO are unique versus other LVDS pins and LVDS is a common differential clock source. Prior Altera/IntelFPGA device families have supported LVDS clock inputs in non-LVDS banks.

I need clarification.

Thanks

-Brian