Is LVDS supported on the dedicated clock input of the Cyclone 10 GX 3.3V IO Bank?

#1 this is Cyclone 10 GX ... not LP.

-- even then, for LP the LVDS receivers in the emulated banks are receivers ... I'd expect dedicated clock inputs to support this.

This is Cyclone 10 GX and we are talking about the dedicated clock inputs. LVDS inputs are powered off of VCCPT which is 1.8V for all IO standards.

from the Handbook ...

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5.7.1.3. Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin

The I/O PLL reference clock (REFCLK) input pin supports the following I/O standards

only:

• Single-ended I/O standards

• LVDS

Intel Cyclone 10 GX devices support Differential HSTL and Differential SSTL input

operation using LVDS input buffers. To support the electrical specifications of

Differential HSTL or Differential SSTL signaling, assign the LVDS I/O standard to the

REFCLK pin in the Intel Quartus Prime software.

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I see differental HSTL/SSTL supported in the 3.3V banks. To use that it says to assign LVDS as the IO Std in Quartus.

Note that this is in regards to dedicated input clock reference pins. There is a difference versus data pins which are clearly not supported in Bank 2L.

Thanks,

-Brian