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Altera_Forum
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8 years ago

Is it possible to implement async ROM/RAM in Stratix family?

Hi, I need to have an asynchronous RAM/ROM in Cyclone IV E for my MIPS processor. Unfortunately, Stratix device family does not support LPM_ROM or LPM_RAM_DQ without providing the inclock/outcl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hello all,

I want to ask about the global and local interconnections in Stratix. In which case I can use almost 100% of the interconnections? I run multiple designs on stratix FPGA, and sometimes the running fails because of either global and local interconnections limitation, however, when I read the reports it say less than 50% in both of them.

I want to understand how interconnections are used in FPGA, if you can help either sending me the links or any suggestions I would appreciate it!

Thanks