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Altera_Forum's avatar
Altera_Forum
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8 years ago

Is it possible to implement async ROM/RAM in Stratix family?

Hi, I need to have an asynchronous RAM/ROM in Cyclone IV E for my MIPS processor. Unfortunately, Stratix device family does not support LPM_ROM or LPM_RAM_DQ without providing the inclock/outcl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The problem is, any build in RAMs in FPGAs are synchronous, so Asynchronous ram will need to be built from logic. Are you really after a fully async ram, or just on the read side?

Have you tried looking at the synthesis templates for inferred rom/ram? What version of quartus are you running?

Quartus should allow initialisation of the ROM using any constant or function call, eg: 


type rom_t is array(0 to 255) of std_logic_vector(7 downto 0);
function init_rom return rom_t is
  variable r : rom_t;
begin
  for i in r'range loop
    r(i) := std_logic_vector( to_unsigned( i, 8) );
  end loop;
  return r;
end function
constant rom  : rom_t := init_rom;