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Altera_Forum's avatar
Altera_Forum
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13 years ago

Is it possible that different paths in a pipelined architecure have differnet latency

If we have 2 pipelines connecting the same stage at the end, it is possible that the two end up having different latency. In this case the stage they both connect to will have to wait for one of them to arrive and for this many clock cycles the faster pipeline shall have to remain idle.

How is such an issue dealt with? How common is it?

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  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If the pipeline delays are fixed (i.e. they are independent from pipelined data) you can simply hold the faster pipeline with the appropriate number or clock cycles.

    If the delays are variable, you surely have a ready signal coming from each pipeline, so you only need to hold the last stage until both ready signals are asserted.

    Anyway the actual solution also depends on the kind of hardware you are dealing with. Infact you may need to redesign the pipeline circuitry in order to provide the required hold functionality.