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Honored Contributor
Honored ContributorIs it OK to use clock in the logic decisions?
I have following logic in the design always @(posedge clkA, posedge clkB) begin if (clkB) //this is like chip select line so it is not nearly as fast as clkA resetAllSignals() ...
Altera_ForumHonored Contributor
Honored ContributorAs this is an SPI protocol, then it is usually much easier to treat clkA as any other logic signal and sample it at a much higher frequency. The Clock_enable is not in any way a clock, so should not be treated as a clock.
