Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Is it OK to use clock in the logic decisions?

I have following logic in the design always @(posedge clkA, posedge clkB) begin if (clkB) //this is like chip select line so it is not nearly as fast as clkA resetAllSignals() ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi Tricky,

Thank you for your response. Could you please elaborate, or point me to the article that explains it, why is it not a good idea? People will ask me why for sure :).

The thing is that the clkB in this case is chip select line so it has to be low before clkA will be turned on for data transfer (regular SPI protocol) so it is not possible to sync clkB with clkA.

Thanks

Ogi