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Altera_Forum
Honored Contributor
Honored ContributorIs it OK to use clock in the logic decisions?
I have following logic in the design always @(posedge clkA, posedge clkB) begin if (clkB) //this is like chip select line so it is not nearly as fast as clkA resetAllSignals() ...
Altera_ForumHonored Contributor
Honored ContributorIf it is a clock - then no, its not a good idea.
If clkB is really slow compared to clkA, then you may be able to get away with it if you treat it as an asynchronous signal, so you synchronise it to ClkA properly, it should be ok.
