Forum Discussion
Altera_Forum
Honored Contributor
10 years agoIn that particular example it *should* be fine, because it is effectively equivalent to:
wire rst_n = !(B & C);
always @ (posedge A or negedge rst_n) begin
if(~rst_n) begin
E <= 0;
end else if (D) begin
E <= F;
end
end
A is still used as the clock, and D is used as a clock enable.