Honored ContributorHi,
i desinged a system in Qsys with multiple devices that have conduit interfaces. One of the devices has a conduit interface (VHDL std_logic_vector). The elements of the standard_logic_vector shall now be connected to the other devices, so that every one of the devices gets one of the elements of the std_logic_vector. Is there a way to do this in Qsys? Thanks, Paddy
Honored ContributorI guess you are asking a way to expose the separate signals out of the Qsys block.
If this is not mandatory, you can easily do the same externally with the following VHDL assignments. You have, for example Qsys_conduit : std_logic_vector(3 downto 0); So, you define: signal_to_device0 <= Qsys_conduit(0); signal_to_device1 <= Qsys_conduit(1); signal_to_device2 <= Qsys_conduit(2); signal_to_device3 <= Qsys_conduit(3);Honored ContributorYes, you are right in what i am asking for. Currently i am doing it the way you showed me, but i thought that there is a way to do it in Qusys internally, without external VHDL-Code.
Honored ContributorI think you can define a custom component based on the original device.
First of all, create wrapper code which implements the division of the standard_logic_vector using the VHDL code above, while it simply connects all the other ports pin to pin. Then in the component _hw.tcl file you expose internal signals with lines like this: add_interface_port conduit_end <internal_signal> export Output 1 I'm almost sure you can do the job with a simple tcl script, without the wrapper, but I'm not very expert on this subject.Honored ContributorOK, i think the idea with a simple VHDL-Wrapper as a Qsys-Module to expose the ports should work for my purposes. A TCL-Script could be something nice for the future, because i only know the basics of the Tcl-scripts...
Thank you very much, Paddy
