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Honored Contributor
Honored Contributoris a PLL needed?
I have never clocked a signal into an FPGA... unitl now and as far as I understand it I need to look at a pin while the clock is high, and clock the value(s) into a register. Where or when would I ne...
Altera_ForumHonored Contributor
Honored ContributorAnother reason to have a PLL in your system, is to zero out the effective clock network delay.
If your data register is located in the IO Buffer, the data path delay to that register may only be the input buffer delay. However the clock delay to that register will have the IO Buffer delay and the clock network delay, which is significant. So this will may cause hold time issues for your data, with respect to clock. With the PLL, you can effectively zero out the clock network delay. Regards, Pete
