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I have never clocked a signal into an FPGA... unitl now and as far as I understand it I need to look at a pin while the clock is high, and clock the value(s) into a register. Where or when would I need to use a PLL?
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Its much easier to distribute a reference clock and then generate higher clock frequencies as needed. For example, communications systems have standard reference clocks (oh, so many standards), eg., 156.25MHz. You can take that frequency and make the obvious integer multiples 2x 312.5MHz, 4x 625MHz, 8x 1250MHz, etc., but you can also divide these higher frequencies to make other values.
A PLL typically consists of;
1) An input divider
2) A phase-frequency detector with a charge-pump (current pulses) output
3) A loop filter (current to voltage conversion)
4) A voltage-controlled oscillator (VCO)
5) A feedback divider
6) Output dividers
Look in the Altera device data sheets and you'll see examples. The VCOs operate over a fairly wide range, but the range still does not cover every frequency you might need, so that is where the output dividers kick in; they'll divide down from where the VCO can operate at, to what you want at the output.
Cheers,
Dave
Honored Contributor
