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Honored ContributorIQ down converting speed
I need some advice on device speeds. I want to implement a simple IQ down converter. A simple test taking an input signal from an A/D (6 clocks to read), & mixing it with an NCO, implemented in a...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- My ADC VHDL state machine needed 6 clocks as it includes the ast signals SOP, EOP, Valid. --- Quote End --- Doesn't sound to be a reasonable way for 65 MHz sampling speed ...
