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Honored Contributor
Honored ContributorIQ down converting speed
I need some advice on device speeds. I want to implement a simple IQ down converter. A simple test taking an input signal from an A/D (6 clocks to read), & mixing it with an NCO, implemented in a...
Altera_ForumHonored Contributor
Honored Contributorthanks all for the input
I am testing using a Straix III dev board with a parrallel single ended adc (65MHz) that i used on another project (only sampling at 4MHz into a cyclone III). My ADC VHDL state machine needed 6 clocks as it includes the ast signals SOP, EOP, Valid (originally 2 channel I & Q). My choice of 10.7MHz IF is simply becuase it is a traditional IF and the RF filtering components are readily available. konrad
