Honored Contributor
Honored ContributorIf that is the case, then it removes the majority of the usefulness of source synchronous mode. I would expect that mode to instruct the fitter to keep the data/clk phase of the internal, zero phase shifted PLL output to be the same. That allows the phase shift parameter to control how far the sample clock edge is into the data window. If the fitter keeps the data/clk phase the same using the the phase shifted output, then there is no way to adjust the sampling edge for an edge-aligned, source sync input. This is counter to the information in AN-433 "Constraining and Analyzing Source Synchronous Interfaces" and "Source Synchronous Timing with TimeQuest" - by Ryan Scoville.
If the PLL is in normal mode, then there is no compensation to compensate for the data/clk path skew. It now has to be done manually by adjusting the PLL phase and any IDELAY blocks in the data path. --- Quote Start --- In PLL source synchronous mode I expect that changing PLL phase will not work as expected since the fitter tries to keep data/clk phase same at any pll phase. I suggest you try PLL in normal mode then adjust its phase. --- Quote End ---
