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Altera_Forum
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8 years ago

IOPLL Source Synchronous Compensation Issue? -- Arria 10

I have a design using a source synchronous input and I am generating the latch clock from an IOPLL in source synchronous compensation mode. The description of that mode states: "If you select th...
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Altera_Forum
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8 years ago

Your setup of timing looks sound to me. What I may differ is the understanding of source synchronous mode for PLL. To me it means the relationship between data and clock at pins is maintained when arriving at io registers.So in your case data is edge aligned but obviously you tell the tool that through set_input_delay(max & min) and I assume then this max/min will be taken into account by the fitter.

edit: notice with several data lines but one clock then compensation has to be optimised or based on a selected line.