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jli125's avatar
jli125
Icon for New Contributor rankNew Contributor
7 years ago

IOPLL in normal mode，output edge and input edge are not aligned

The device is Arria 10. IOPLL input clk freq is 100M，output0 is 100M and output1 is 800M. Output0 is used as an internal clock. In the image，this is the SignalTap screenshot，and sampling clock is ou...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hi , Kinldy check, is there any phase sift is provided in the PLL IP. Mostly this will happens because of phase shift. Regards, Rs