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Altera_Forum's avatar
Altera_Forum
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13 years ago

IOE Programmable Delay

Hello,

The data sheets for the FPGAs list the IOE programmable delays as follows (generic example):

Parameter: D1

Available Settings: n

Min Offset: 0

Fast Model: x ns

Slow Model: y ns

Could someone please shed some light on the Available Settings n parameter?

Does the delay setting need to be n all the time? Can it be less than that? If the delay setting is 1, what is the effective delay?

Thank you!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    There should be a note below the table that you are looking at.

    As an example, the Cyclone IV sheet says:

    --- Quote Start ---

    (1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.

    --- Quote End ---

    Which means that there are "n" roughly linearly spaced steps from 0 to x/y for the delay in question (using your terminology). In other words, you've got "n" choices of what you want the setting to be, and the exact value is TBD (compile with the latest quartus and find out after the fact what it says you got).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks Ted! That makes sense.

    I am assuming that the fast model and slow model numbers are upper and lower limits for PVT. Is that correct?