Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorIOE Programmable Delay
Hello, The data sheets for the FPGAs list the IOE programmable delays as follows (generic example): Parameter: D1 Available Settings: n Min Offset: 0 Fast Model: x ns Slow Model: y...
Altera_ForumHonored Contributor
Honored ContributorThanks Ted! That makes sense.
I am assuming that the fast model and slow model numbers are upper and lower limits for PVT. Is that correct?
