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Altera_Forum
Honored Contributor
Honored ContributorIOBuff Usage
Hi, I have input to output direct mapping in my design. I am not able to time close it to 5ns because of IC Delay. input is in 3.3 V domain: set_instance_assignment -name IO_STANDARD "3....
Altera_ForumHonored Contributor
Honored ContributorHi,
Screenshot of chip planner view and path delay report is attached here. Thanks, Neeraj
