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Altera_Forum's avatar
Altera_Forum
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8 years ago

IOBuff Usage

Hi, I have input to output direct mapping in my design. I am not able to time close it to 5ns because of IC Delay. input is in 3.3 V domain: set_instance_assignment -name IO_STANDARD "3....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

There's no logic between the input and the output? Strange.

I'd check the Chip Planner and the Fitter Information tab in a detailed timing report to try to figure out why the Fitter routed this path so poorly. There must be some physical placement requirement that is causing the delay.

Also, how full is your device?