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Altera_Forum
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14 years ago

I/O states in Cyclone III in JTAG mode

Hello all, In Altera's application notes it is specified that during JTAG mode all I/O pins are tristated. It is sometimes mentioned that the weak pull ups are enabled when the I/O pins are t...
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Altera_Forum
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14 years ago

Altera preferred to omit the clearer description in previous device handbook versions.

Now the information is hidden in Note (1) to table 12-3:

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Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.

--- Quote End ---

In previous versions, there was an explicite explanation of individual BST instructions affecting the IO states, e.g. for CLAMP:

--- Quote Start ---

If you are testing after configuring the device, the programmable weak pull-up resistor or the bus hold feature overrides the CLAMP value (the value stored in the update register of the boundary-scan cell) at the pin.

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In any case, if you are in doubt about the real device behaviour, why don't you simply try it?