Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I/O states in Cyclone III in JTAG mode

Hello all, In Altera's application notes it is specified that during JTAG mode all I/O pins are tristated. It is sometimes mentioned that the weak pull ups are enabled when the I/O pins are t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi Daixiwen,

By "JTAG MODE" I'm referring to the test state in which JTAG tests are being run on the Cyclone III chip.

Does your answer cover this state?

Thanks,

Boris.