Altera_Forum
Honored Contributor
14 years agoI/O Pin voltage
Hello,
I am trying to design a simple multiplexer using the Cyclone III FPGA on the DE0 board. I am using the PLL to divide the 50MHz on board clock down to the appropriate speed. However whenever I try to put a signal out to one of the I/O pins, it is only about 20mV peak to peak. I understand the pins on the DE0 board should put out 3.3V. I have the pins assigned to the 3.3V standard in the Quartus II pin planner, but it doesn't seem to make any difference. Any help would be appreciated.