I/O D1/D3 delay values higher than needed.

Hi Anand.

Finally me and my colleague "successfully" recreated the issue in a simple test project.

The project on its top-level consists of three parts - CLOCK, ETHERNET and a simple DAC part.

CLOCK consists of two PLLs, first PLL is for all clocks used in project, and second is for RX part of ETHERNET only, it receives rx_clock from TSE rx and in Source Synchronous Mode outputs clock for latching the RX data to the appropriate I/Os.

ETHERNET consists of triple speed ethernet core and DDIO for TX clock output.

DAC consists of a very simple bunch of code, and the most interesting thing is that it is clocked by 200 MHz clock by default.

So the issue which I mentioned in the beginning of that post was recreated.

We also found what action should be done for the issue to disappear - we changed the source clock for DAC part from 200 to 100 MHz and the result is on the picture below:

So the interesting part of an issue is that there is another block whose source clock comes from another PLL has an impact on timing (in particular the I/O internal delay values). As I previously mentioned we can correct I/O internal delay values manually and obtain the correct timing.

I attached the project.

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Best regards,

Ivan