I/O D1/D3 delay values higher than needed.

Hi Anand.

Thank you for your reply.

Yes, I know that Quartus can program these delays, and it programs them indeed in my project, and I want Quartus to do that automatically following my constraints.

Because I exploit constraints, and also I use DDIO, D1/D3 delay values are the way for Quartus to pass timing.

So my problem is - I wrote constraints like this (as it is in example done by Ryan Scoville in Source Synchronous wiki examples):

create_clock -period 8.0 -name ssync_rx_clk [get_ports ssync_rx_clk] -waveform {2.0 6.0}

create_clock -period 8.0 -name ssync_clk_ext

derive_pll_clocks

derive_clock_uncertainty

set_input_delay -clock ssync_clk_ext -max 0.5 [get_ports {ssync_rx_data[*]}]

set_input_delay -clock ssync_clk_ext -min -0.5 [get_ports {ssync_rx_data[*]}]

set_input_delay -clock ssync_clk_ext -max 0.5 [get_ports {ssync_rx_data[*]}] -clock_fall -add_delay

set_input_delay -clock ssync_clk_ext -min -0.5 [get_ports {ssync_rx_data[*]}] -clock_fall -add_delay

set_false_path -fall_from [get_clocks ssync_clk_ext ] -rise_to [get_clocks inst1|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk] -setup

set_false_path -rise_from [get_clocks ssync_clk_ext ] -fall_to [get_clocks inst1|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk] -setup

set_false_path -rise_from [get_clocks ssync_clk_ext ] -rise_to [get_clocks inst1|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk] -hold

set_false_path -fall_from [get_clocks ssync_clk_ext ] -fall_to [get_clocks inst1|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk] -hold

I also use a PLL in source synchronous mode.

I checked them, and I received negative setup slacks on input ports as can be seen in my first post, fig 1.

After that, I inspected failed paths, and I realized that Quartus set I/O D1/D3 delays in such way, that timing fails, but then I had manually chosen different values, timing passed.

So, my question is, why Quartus decided to choose "wrong" delay values?

Thank you.

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Best regards,

Ivan