IO buffers

Yes the flip flop does feed too many mux and mux only and then the mux out is being drived to the output and yes i am facing timing issues to a bigger extent.

Actually the code wasnt written by me i have to do the synthesis only.

Just tell me one thing can a path such as

Flop->mux->output a desirable logic.

i doubt that since a combo logic is feeding the outputs it maybe a reason for larger delays.

And ya the clock to the module i am constraining is 225Mhz.

It will be helpful for me if u can comment on this. :)