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Altera_Forum's avatar
Altera_Forum
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14 years ago

IO buffers

Hi guys i am doing synthesis at module level and IO buffers are being implemented by the tool.. I dont want these buffers to be implemented. Can anybody help me with the constraints for not infe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hii thanks for the reply.

But just wanted to know one thing like the output ports of my module are being buffered and are causing the delays for example the one in the image below...

So just clarifying that can i define my output ports as virtual??