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KeeganJ's avatar
KeeganJ
Icon for New Contributor rankNew Contributor
3 years ago
Solved

I/O Bank choice for 64 bit wide EMIF on Cyclone 10 (GX)

I'm having trouble determining what is the optimal pin assignment for a 64-bit wide EMIF interface at 933 MHz. I'm using the 780-pin device. I know the EMIF will require 3 banks, all in one I/O col...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi KeeganJ,


    Thank you for submitting you question in Intel Community,

    I'm Adzim, application engineer will assist you in this thread.


    You have right understanding on IO banks usage.

    I also would like to suggest to use "Option One" because you can use termination on LVDS IO bank.

    The VCCIO for DDR3 protocol must be driven at 1.5V.

    You need to make sure the voltage is correct for every IO banks that have been used for EMIF IP.


    The option below is correct.

    - Option One: 2A (data), 2J (addr/command), 2K (data)


    Regards,

    Adzim



AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi KeeganJ,


Thank you for submitting you question in Intel Community,

I'm Adzim, application engineer will assist you in this thread.


You have right understanding on IO banks usage.

I also would like to suggest to use "Option One" because you can use termination on LVDS IO bank.

The VCCIO for DDR3 protocol must be driven at 1.5V.

You need to make sure the voltage is correct for every IO banks that have been used for EMIF IP.


The option below is correct.

- Option One: 2A (data), 2J (addr/command), 2K (data)


Regards,

Adzim