Honored Contributor
Honored ContributorI've sometimes found with densely packed Cyclone I and II designs that I can have a few free LEs but no (or not enough) LABs. This is usually because the design is limited by routing requirements.
Basically you end up with the problem that you make a really minor change and the design can't route - there is enough logic space to add that extra LE (or ALM) but no way to get the signal in and out because all the LABs have their routing resources (carries, clks etc) already taken up. --- Quote Start --- I have added some large functions and the bottom line has gone up by less than I would have anticipated. Is this a good sign? --- Quote End --- It depends - if those large functions are closely related to other stuff that is already in then you might be able to infer that there isn't a huge impact on the routing. If you try adding something completely unrelated then you might find you have a problem. The key here is risk analysis: You don't necessarily have a problem. How complete is your design and what is the likelihood of having to make a change? If you've done tonnes and tonnes of simulation and the design has been through all its testing phases and accepted by customers then you might decide the cost saving of sticking with the smaller device outweighs the risk of a change leading to the design not fitting. You said you meet timing OK - is this a large margin? - if it is a tight margin then you may have to consider that design tweaks may impact the timing and you end up having to insert a whole new level of pipelining which pushes you over the edge. If on the other hand you've easily met the timing requirements then this probably isn't a worry. What synthesis / fitter settings have you used? Optimise for timing / size Resource sharing automatically removing duplicate logic and registers (reduces logic count but can impact routing) Register packing (same comment) Auto insert logic / registers (can aid routing at the expense of using more logic) One of my designs I ended up having to set all the logic reduction settings to maximum and then tell the compiler to add in more where it needed. This slight paradox meant that it packed the design as tightly as it could but then added just what it needed in order to get the routing done. Have a contingency plan - sk what you are going to do if you suddenly find that the design won't fit: Is the next device up pin compatible? (I think yes from the info you provided) Are there any bits of the design that you could rip out if need be? - e.g. do you have some debugging logic that is useful for development but can come out of the production issue? Rather than jumping in price to the next biggest Stratix is there some function(s) that you could pull out into a much smaller (and cheaper) FPGA, PLD or micro? (probably not given the size of the device that you have). If you're at the design stage and just building a couple of boards you could build them with the bigger device just so you can get the design done without worrying about space - prove your design and your function and then try to get it to fit in the smaller device for production which (hopefully) would mean not changing the board layout. Hope this helps.
