Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Internally generated clock (VHDL)

If I generate a clock within a MAXII pld, I can output that signal to a pin, wire the pin to a spare global clock input and use it without problem.

How do I do this connection internally without having to add a wire. How do I connect an internal node to a global clock line? (I'm trying to do this in VHDL).

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I don't understand your post. The Quartus fitter selects MAX II global clock signals automatically for respective signals, e.g. if you create a ripple clock, you can check in the fitter report resource section.