Internal LVDS for between-board communicatino

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Yes, if I provide the clock I don't need to encode the data. No bad effects will happen if a AC-coupled line stays high for too long ?

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In most AC coupling schemes, it is important for the time average of the signal to be equal (or nearly equal) to the common mode voltage (ie. the same number of zeros and ones over some time span). If a constant value is held for too long, it will behave like DC, and will be filtered by the coupling circuit so that the receiver sees 0V differential.

One way around this is to use 8b10b or similar encoding (yes, even if you are not doing clock recovery), as it guarantees DC balancing. This encoding scheme is not that complicated, and at your frequency, does not require any dedicated hardware. The complicated part would be the clock recovery, but you are not doing that.

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I don't claim to know your system enviroment in detail, but a LVDS connection without a acompanying signal ground has a high risc of catching interferences, with or without AC coupling. Also possible damage to the FPGA IOs must be feared.

You have to consider also higher frequecy interferences, not only DC and mains frequency potential differences. Would be different when using a transformer coupling, e. g. by ethernet magnetics. But this also requires 8b/10b, as suggested.

Another (DC capable) solution is to use digital isolators from NVE or Analog.

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Thanks for all the help :)

I don't claim to know your system enviroment in detail, but a LVDS connection without a acompanying signal ground has a high risc of catching interferences, with or without AC coupling. Also possible damage to the FPGA IOs must be feared.

You have to consider also higher frequecy interferences, not only DC and mains frequency potential differences. Would be different when using a transformer coupling, e. g. by ethernet magnetics. But this also requires 8b/10b, as suggested.

Another (DC capable) solution is to use digital isolators from NVE or Analog.

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Whoa let's not make this too complicated. If your grounds are seperated with no way of making them common, then yes your best bet is to run differential. If your grounds are not related to each other in some way, then you have absolutely no way of knowing what the potential between the two is.

However remember we're only talking 40Mbps here. Run four traces (a differential clock and a differential data signal). Use AC coupling caps on the traces (preferably close to the receiver). And use a simple DC-biased termination scheme.

If you provide the clock, there is absolutely no need to encode the data. Encoding schemes like 8b/10b are designed to provide a maximum number of transitions to allow for easier clock data recover at the receiver. Just provide the clock.

I assume that your boards have been layed out with differential traces?

Jake

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Yes, if I provide the clock I don't need to encode the data. No bad effects will happen if a AC-coupled line stays high for too long ?

My boards are in the design phase, and we plan to use differential traces, yes.

Whoa let's not make this too complicated. If your grounds are seperated with no way of making them common, then yes your best bet is to run differential. If your grounds are not related to each other in some way, then you have absolutely no way of knowing what the potential between the two is.

However remember we're only talking 40Mbps here. Run four traces (a differential clock and a differential data signal). Use AC coupling caps on the traces (preferably close to the receiver). And use a simple DC-biased termination scheme.

If you provide the clock, there is absolutely no need to encode the data. Encoding schemes like 8b/10b are designed to provide a maximum number of transitions to allow for easier clock data recover at the receiver. Just provide the clock.

I assume that your boards have been layed out with differential traces?

Jake

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A problem may arise, when the LVDS signal ground is the only ground connection between the two systems or even the only existing ground connection at all. Then high intereference currents are attracted by this connection. An additional ground connection and a common mode choke including all data lines and the signal ground (e. g. a ferrite core around the cable) may be advisable.

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I don't understand - how does this work out with distant enclusures connected with LVDS between them ? They have absolutely no common ground (except Earth), and no other signals except the LVDS between them.

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The two boards do share a common chassis, but their operating voltages and grounds are generated by separate isolated DC/DC converters. Their grounds are definitely close enough to not require AC coupling on the transmission lines.

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A problem may arise, when the LVDS signal ground is the only ground connection between the two systems or even the only existing ground connection at all. Then high intereference currents are attracted by this connection. An additional ground connection and a common mode choke including all data lines and the signal ground (e. g. a ferrite core around the cable) may be advisable.

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I would expect a common ground and also ground connection together with the data lines. Otherwise the said transformer coupling would be necessary to guarantee an input voltage within receiver common mode range. Then you move far away from an easy interface, clock recovery and data resynchronisation from 8b/10b encoded data is supported by dedicated hardware only for gigabit I/O standards. It may be possibly achieved utilizing the DPA block and additional logic, but not easily.

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The two boards do share a common chassis, but their operating voltages and grounds are generated by separate isolated DC/DC converters. Their grounds are definitely close enough to not require AC coupling on the transmission lines.

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I've been often using a standard SPI (Motorola defined) interface. The CS acts as sync or frame clock in this case, just a shift register is the basic logic needed for receiver and transmitter.

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I see, so it's the basic SPI that's used with, say, ADCs and various sensors.

Thanks for the tips.

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Just how disconnected are your ground domains? If they are not connected at all, you will want to AC couple the LVDS signal lines, at least with capacitors, if not a transformer.

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I would expect a common ground and also ground connection together with the data lines. Otherwise the said transformer coupling would be necessary to guarantee an input voltage within receiver common mode range. Then you move far away from an easy interface, clock recovery and data resynchronisation from 8b/10b encoded data is supported by dedicated hardware only for gigabit I/O standards. It may be possibly achieved utilizing the DPA block and additional logic, but not easily.

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Do you refer to the Serial Peripheral Interface SPI ? Because it doesn't have a separate frame sync signal?

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I've been often using a standard SPI (Motorola defined) interface. The CS acts as sync or frame clock in this case, just a shift register is the basic logic needed for receiver and transmitter.

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Thanks for the tips. My motivation to go for LVDS stems from electrical requirements, and not particularly speed. The two cards' digital grounds are not shorted together, and differential is the best way I can see to transfer data between them.

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Just how disconnected are your ground domains? If they are not connected at all, you will want to AC couple the LVDS signal lines, at least with capacitors, if not a transformer. An encoding scheme such as 8b10b will then be required to prevent DC drift on the AC coupling components.