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Altera_Forum
Honored Contributor
18 years agoInternal LVDS for between-board communicatino
Hello, Suppose that I have two boards with Stratix II FPGAs. The boards sit close to each other, and lines from one FPGA reach the other, via a connector. The total length is circa 20 cm (8 inc...
Altera_Forum
Honored Contributor
18 years ago --- Quote Start --- Yes, if I provide the clock I don't need to encode the data. No bad effects will happen if a AC-coupled line stays high for too long ? --- Quote End --- In most AC coupling schemes, it is important for the time average of the signal to be equal (or nearly equal) to the common mode voltage (ie. the same number of zeros and ones over some time span). If a constant value is held for too long, it will behave like DC, and will be filtered by the coupling circuit so that the receiver sees 0V differential. One way around this is to use 8b10b or similar encoding (yes, even if you are not doing clock recovery), as it guarantees DC balancing. This encoding scheme is not that complicated, and at your frequency, does not require any dedicated hardware. The complicated part would be the clock recovery, but you are not doing that.