interleave two AD9481 with fpga PLL

There are another couple of options;

1. You could take a single differential clock from the FPGA and route it to a clock buffer with 1:2 fanout. Then swap the differential signals for the second ADC's clock; that will invert its clock, relative to the first ADC.

2. Use a part that can be clocked at 500MHz. TI have parts, e2v have parts. Clock it with an external VCO.

Be very careful with the clocks from the FPGA. They are not designed for use with 'analog' signals. The clock to an ADC is like an analog mixer. Any clock noise and harmonics will show up in the sampled signal. Before even considering using an FPGA clock in this manner, you should look to see how good the FPGA PLL output clock phase noise is.

Cheers,

Dave