interleave two AD9481 with fpga PLL

As you should know, guaranteeing that the clocks that reach both ADCs are exacly 180º apart is crucial.

Quite honestly, I'm not sure if the FGPA can guarantee this to the level of your requirements.

You'll need to test before committing to a desing.

Each PLL can generate multiple clocks, but it only has 1 dedicated low skew output pin.

If you need two outputs, you need to use the general output pins which have more skew.

So, a few option...

Option 1:

You already have an external 0º clock. Use a PLL in zero delay mode to generate a 180º clock and output it via the PLL's dedicated output pin.

Option 2:

Use a PLL to generate both 0º and 180 ºclocks and drive them out through general purpose I/O pins.

Option 3:

Use two PLLs to generate the 0º and 180º clocks and use each PLL's dedicated output pins.

In any case, you can try to adjust the phase of the PLL generated clocks to have an exact 0º and 180º clock at the ADCs.