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Honored Contributor
8 years agoHi Alex,
Thank you very much for your response. Indeed I am very new to Altera FPGAs so I guess I am doing something stupid. :) MSEL is indeed configured for AS mode. That was our initial intention. However we are able to program the FPGA from the PC thru FTDI FT4232H emulating the JTAG. Our board is always connected to a PC and on each board boot we load teh configuration from a PC and this method is convenient for us now. I have not constrained the EPCS pins! I have assumed that those pins are special as I didn't manage to find anything about those pins in the IP parameter Editor for the "Altera ASMI Parallel" block I guess here is the key. I will try to study the topic some more. Under 'Dual-Purpose Pins' I have two groups Data[0] and Data[7..1] both set to "Use as regular I/O" , so I guess I am OK here. Thank you once again. Dimitar